I wanna design a processor architecture.
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bonifartius πΌπ 
I totally have an idea in mind.
You know the belt from the MILL processor design?
It's that, except reversed.
So each instruction pulls K operands off position 0 of the belt, and there's 1 index in the instruction, and that's the location of the output that will be written to the belt.
Far out the belt is DRAM, close up is cache.
You know the belt from the MILL processor design?
It's that, except reversed.
So each instruction pulls K operands off position 0 of the belt, and there's 1 index in the instruction, and that's the location of the output that will be written to the belt.
Far out the belt is DRAM, close up is cache.
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@cjd didn't know about mill design, looks interesting on a cursory read.
at uni we did this with programmable logic gates (iirc), very 80s :) but pretty good fun, certainly easy to build a small calculator like poc with those.
at uni we did this with programmable logic gates (iirc), very 80s :) but pretty good fun, certainly easy to build a small calculator like poc with those.
@cjd i have no clue but from what i've read isn't the belt supposed to be read only save appending to the tail to prevent problems?
In MILL's design, your return value always writes to slot 0 and the belt shifts "away" from you. And instructions have 2 indexes which can select any 2 positions on the belt to grab operands from. And when something falls off the end of the belt, it's lost.
In my design, the belt moves "toward you", meaning the next instruction is going to pull 2 operands off the belt. And the return value is the one you get to decide where on the belt it will fall. So in my design, it's your job to setup the belt so that operands arrive at slot 0 at the same time as when the instruction that needs them gets executed.
In my design, the belt moves "toward you", meaning the next instruction is going to pull 2 operands off the belt. And the return value is the one you get to decide where on the belt it will fall. So in my design, it's your job to setup the belt so that operands arrive at slot 0 at the same time as when the instruction that needs them gets executed.