I wanna design a processor architecture.
Timeline
Post
Remote status
Context
3
bonifartius πΌπ 
@cjd did design a very small cpu/computer at uni, that was fun :)
I totally have an idea in mind.
You know the belt from the MILL processor design?
It's that, except reversed.
So each instruction pulls K operands off position 0 of the belt, and there's 1 index in the instruction, and that's the location of the output that will be written to the belt.
Far out the belt is DRAM, close up is cache.
You know the belt from the MILL processor design?
It's that, except reversed.
So each instruction pulls K operands off position 0 of the belt, and there's 1 index in the instruction, and that's the location of the output that will be written to the belt.
Far out the belt is DRAM, close up is cache.
@cjd didn't know about mill design, looks interesting on a cursory read.
at uni we did this with programmable logic gates (iirc), very 80s :) but pretty good fun, certainly easy to build a small calculator like poc with those.
at uni we did this with programmable logic gates (iirc), very 80s :) but pretty good fun, certainly easy to build a small calculator like poc with those.
Replies
0
No replies yet.